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A few questions regarding timing analysis

elektroda.net NewsGroups Forum Index - Verilog Language - A few questions regarding timing analysis

Daku
Guest

Mon Jun 21, 2010 7:23 am   



Could some Verilog guru please clarify
a few points regarding my problem ? I
have modelled a content-addressable
memory block, with parallel search, and
I am trying to measure number of clock
cycles for to insert a word and parallel
search for a word.
Both of insert and search operations are blocking and asynchronous.
These two
operations are triggered with 'write_en'
and 'search_en' going high respectively.
A clock runs separately and in the case
both 'write_en' and 'search_en' are low
and clock is high, some book-keeping
operations are performed.
Given this setup, how do I measure the
time required for an insertion and the
time for a search ? I am fully aware of
the standard Verilog command '$time'
and specifically may I know if taking
time-stamps before start of an operation
and immediately after the end, would be
sufficient.
Any hints, suggestions would be of immense
value. Thanks in advance for your help.

d_s_klein
Guest

Wed Jun 23, 2010 9:27 pm   



If I understand your post, you have built an asynchronous (non-
synchronous) simulation model of a CAM using blocking assignment
variables.

In a simulation model like this, $time has no meaning.

RK

On Jun 20, 9:23 pm, Daku <dakup...@gmail.com> wrote:
Quote:
Could some Verilog guru please clarify
a few points regarding my problem ? I
have modelled a content-addressable
memory block, with parallel search, and
I am trying to measure number of clock
cycles for to insert a word and parallel
search for a word.
Both of insert and search operations are blocking and asynchronous.
These two
operations are triggered with 'write_en'
and 'search_en' going high respectively.
A clock runs separately and in the case
both 'write_en' and 'search_en' are low
and clock is high, some book-keeping
operations are performed.
Given this setup, how do I measure the
time required for an insertion and the
time for a search ? I am fully aware of
the standard Verilog command '$time'
and specifically may I know if taking
time-stamps before start of an operation
and immediately after the end, would be
sufficient.
Any hints, suggestions would be of immense
value. Thanks in advance for your help.


elektroda.net NewsGroups Forum Index - Verilog Language - A few questions regarding timing analysis

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