majmoat_ensan
Guest
Sun Jul 17, 2011 2:31 am
Hi all,
I am tried to write VHDL code for 1 to 8 Demux and that's what i
finish with it
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN STD_LOGIC;
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to2;
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
G1: FOR i IN 0 TO 1 GENERATE
Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
G2: FOR i IN 2 TO 5 GENERATE
Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
END GENERATE ;
END GENERATE ;
Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
7) );
END Structure;
can any one told me if is it right or not?
if there are any mistakes can you help me to correct it ?
Nicolas Matringe
Guest
Sun Jul 17, 2011 7:48 am
Le 17/07/2011 03:02, majmoat_ensan a écrit :
Quote:
Hi all,
Hi
Quote:
I am tried to write VHDL code for 1 to 8 Demux and that's what i
finish with it
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Do NOT use non-standard libraries like std_logic_arith, std_logic_signed
or std_logic_unsigned. Use numeric_std instead.
Quote:
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN STD_LOGIC;
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to2;
Although it doesn't change anything in terms of behaviour, it is common
practice to declare vectors with a descending range (e.g. 7 downto 0)
because the higher index bit is then the leftmost bit (which helps a lot
when you use arithmetic vectors)
Quote:
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
G1: FOR i IN 0 TO 1 GENERATE
Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
G2: FOR i IN 2 TO 5 GENERATE
Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
END GENERATE ;
END GENERATE ;
Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
7) );
There are spaces in your (intended) component name. You can't do this.
Besides, it is also common practice to use named association for port
maps because it is much less error prone (but is adds a lot of typing
unless you use an Editor with MACroS)
Quote:
END Structure;
It is absolutely impossible to say if this is good or not because you
don't give the code for components demux1to2 and demux1to8. I find it
strange that you map the same demux1to2 component with 3 ports in your
first generate loop and only 2 ports in the second one.
Nicolas
Rob Gaddi
Guest
Mon Jul 18, 2011 4:24 pm
On 7/17/2011 12:48 AM, Nicolas Matringe wrote:
Quote:
Le 17/07/2011 03:02, majmoat_ensan a écrit :
Hi all,
Hi
I am tried to write VHDL code for 1 to 8 Demux and that's what i
finish with it
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Do NOT use non-standard libraries like std_logic_arith, std_logic_signed
or std_logic_unsigned. Use numeric_std instead.
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN STD_LOGIC;
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to2;
Although it doesn't change anything in terms of behaviour, it is common
practice to declare vectors with a descending range (e.g. 7 downto 0)
because the higher index bit is then the leftmost bit (which helps a lot
when you use arithmetic vectors)
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
G1: FOR i IN 0 TO 1 GENERATE
Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
G2: FOR i IN 2 TO 5 GENERATE
Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
END GENERATE ;
END GENERATE ;
Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
7) );
There are spaces in your (intended) component name. You can't do this.
Besides, it is also common practice to use named association for port
maps because it is much less error prone (but is adds a lot of typing
unless you use an Editor with MACroS)
END Structure;
It is absolutely impossible to say if this is good or not because you
don't give the code for components demux1to2 and demux1to8. I find it
strange that you map the same demux1to2 component with 3 ports in your
first generate loop and only 2 ports in the second one.
Nicolas
Also, you reused 'i' as your loop variable in the inner loop.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Rob Gaddi
Guest
Wed Jul 20, 2011 4:35 pm
On 7/20/2011 7:48 AM, majmoat_ensan wrote:
Quote:
[snip]
ummm if i tried to wrote it in this way is it right or not?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to8;
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
Dmux1: Dmux1to8 PORT MAP
( X, s(0), m(0), m(1) ) ;
Dmux2: Dmux1to8 PORT MAP
( m(0), s(1), m(2), m(3) ) ;
Dmux3: Dmux1to8 PORT MAP
( m(1), s(1), m(4), m(5) ) ;
Dmux4: Dmux1to8 PORT MAP
( m(2), s(2), w(0), w(1) ) ;
Dmux5: Dmux1to8 PORT MAP
( m(3), s(2), w(2), w(3) ) ;
Dmux6: Dmux1to8 PORT MAP
( m(4), s(2), w(4), w(5) ) ;
Dmux7: Dmux1to8 PORT MAP
( m(5), s(2), w(6), w(7) ) ;
END Structure ;
No, now you're trying to recursively instantiate the element inside of
itself.
What on earth are you actually trying to accomplish, and why are you
trying to build something as simple as a demux with anything inside of
it? Just write the stupid thing in RTL. Honestly even that borders on
the insane, the RTL demux should just be written directly into whatever
higher level block it was going to go into.
http://lmgtfy.com/?q=demultiplexer+vhdl
--
Rob Gaddi, Highland Technology
Email address is currently out of order
majmoat_ensan
Guest
Wed Jul 20, 2011 4:48 pm
On Jul 18, 7:24 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
Quote:
On 7/17/2011 12:48 AM, Nicolas Matringe wrote:
Le 17/07/2011 03:02, majmoat_ensan a écrit :
Hi all,
Hi
I am tried to write VHDL code for 1 to 8 Demux and that's what i
finish with it
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Do NOT use non-standard libraries like std_logic_arith, std_logic_signed
or std_logic_unsigned. Use numeric_std instead.
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN STD_LOGIC;
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to2;
Although it doesn't change anything in terms of behaviour, it is common
practice to declare vectors with a descending range (e.g. 7 downto 0)
because the higher index bit is then the leftmost bit (which helps a lot
when you use arithmetic vectors)
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
G1: FOR i IN 0 TO 1 GENERATE
Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
G2: FOR i IN 2 TO 5 GENERATE
Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
END GENERATE ;
END GENERATE ;
Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
7) );
There are spaces in your (intended) component name. You can't do this.
Besides, it is also common practice to use named association for port
maps because it is much less error prone (but is adds a lot of typing
unless you use an Editor with MACroS)
END Structure;
It is absolutely impossible to say if this is good or not because you
don't give the code for components demux1to2 and demux1to8. I find it
strange that you map the same demux1to2 component with 3 ports in your
first generate loop and only 2 ports in the second one.
Nicolas
Also, you reused 'i' as your loop variable in the inner loop.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
ummm if i tried to wrote it in this way is it right or not?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to8;
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
Dmux1: Dmux1to8 PORT MAP
( X, s(0), m(0), m(1) ) ;
Dmux2: Dmux1to8 PORT MAP
( m(0), s(1), m(2), m(3) ) ;
Dmux3: Dmux1to8 PORT MAP
( m(1), s(1), m(4), m(5) ) ;
Dmux4: Dmux1to8 PORT MAP
( m(2), s(2), w(0), w(1) ) ;
Dmux5: Dmux1to8 PORT MAP
( m(3), s(2), w(2), w(3) ) ;
Dmux6: Dmux1to8 PORT MAP
( m(4), s(2), w(4), w(5) ) ;
Dmux7: Dmux1to8 PORT MAP
( m(5), s(2), w(6), w(7) ) ;
END Structure ;
KJ
Guest
Wed Jul 20, 2011 10:59 pm
On Jul 20, 12:35 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
Quote:
What on earth are you actually trying to accomplish
Homework perhaps.
KJ
Guest
Thu Jul 21, 2011 2:31 am
On Jul 20, 10:48 am, majmoat_ensan <majmoat_en...@windowslive.com>
wrote:
Quote:
ummm if i tried to wrote it in this way is it right or not?
Not.
Not even close (to be more precise)
Consider downloading either a free version of Modelsim or GHDL and
start compiling and simulating your code. The tool will give you must
quicker and more detailed responses to your questions...it will also
let you simulate your design to see if it works as you intend.
Learning by doing is a very effective method.
Kevin Jennings
